In the manufacture of microelectronics, circuits and other logic must be placed on chips under certain wirability and timing constraints. Specifically, the electric circuits must be placed in such a way that the wiring interconnects between the cells are within the wiring constraints of the chip. Moreover, the wiring interconnects between the cells cannot be placed arbitrarily close to each other. Rather, a certain wiring pitch must be observed. Placement of cells on a chip is especially problematic when the wiring requirements between the electric circuits approach the wiring availability. In these situations, the resulting wiring congestion can cause “hot spots” on the chip which make the design unwirable. Therefore, it is necessary to optimize the placement of cells on the chip so that the available wiring space matches the routing requirements.
Attempts have been made to provide improved circuit placement. In general, such attempts begin by positioning cells (typically including circuits, transistors and other elements) on a chip while minimizing the sum of the squared net length. Subsequently, the chip is then divided/partitioned into a first placement level having four bins or quadrants. The cells are then arranged in the four bins. Next, each of the four bins are partitioned into a second placement level having four sub-bins, and the cells for each bin are arranged in the corresponding sub-bins. The process can then be repeated for subsequent placement levels until a minimum bin size is reached. Although this allows the cells to be physically positioned on the chip, it does not guarantee a wirable chip placement. To provide a wirable chip placement, a user must subsequently either manually identify the positioned logic nodes that cause wiring congestion and reduce the circuit density accordingly, or reduce the overall chip density by increasing the chip size. In the case of the former, several time-consuming iterations are required. In the case of the latter, increasing the chip size will lead to a substantial increase in cost.
The U.S. Pat. No. 6,904,584 B2 discloses a method and a system for placing cells based on an estimated wiring congestion. In congested areas the placement density is reduced, thus reducing the original congestion problem. The output of this placement is an assignment of cells to placement bins. In a final detailed placement step cells are legally placed inside the designated placement bins. Since cells are usually blocked on the first wiring layer M1 by a major portion of their area, this results in a highly fragmented routing space on the first wiring layer which can hardly be used by a routing tool. Due to the high number of first wiring layer shapes and since the first wiring layer cannot be used for significant routing anyway, many modern routers use the first wiring layer M1 strictly for pin access to considerably improve the router's runtime behavior. In typical standard cells of a 90 nm design, the placement densities are between 60 to 70%. Hence, a significant amount of routing space is given up. But even if the router would use the first wiring layer routing resources, the fragmented nature of the placement only allows very short segments that do not improve wireability. Additional vias are needed to wire down into the empty first wiring layer area and back again.
In view of the foregoing, there is a need for a method and a system for placing logic nodes on a chip in such a way as to improve wiring and make better use of the routing resources of the first wiring layer M1.